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| author | Peter Maydell <peter.maydell@linaro.org> | 2012-05-02 16:49:40 +0000 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-06-19 13:24:44 +0000 |
| commit | 6b9680bb5826dcf0ead42bafb62946f472466d63 (patch) | |
| tree | 8ca295252fa148d6222adef9592e778a2d3d94e4 /scripts | |
| parent | 306a571a2d75e32cd2eae5486c2714b7b7792a63 (diff) | |
| download | focaccia-qemu-6b9680bb5826dcf0ead42bafb62946f472466d63.tar.gz focaccia-qemu-6b9680bb5826dcf0ead42bafb62946f472466d63.zip | |
hw/arm_gic: Make CPU target registers RAZ/WI on uniprocessor
The GIC spec says that the CPU target registers should RAZ/WI for uniprocessor implementations. Implement this, which also conveniently lets us drop an NVIC ifdef. Annoyingly, the 11MPCore's GIC is the odd one out, since it always has these registers, even in uniprocessor configs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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