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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-04-28 11:31:04 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-06-28 04:35:07 +0530 |
| commit | ef9c5ea85d83459361449259418726a5d4d0a751 (patch) | |
| tree | 6c7ff32f41eca02c8fbf7ad07cd4fd93149f02a5 /semihosting/arm-compat-semi.c | |
| parent | cd7f29e335a88c2803bfb42ee3cef60417c43274 (diff) | |
| download | focaccia-qemu-ef9c5ea85d83459361449259418726a5d4d0a751.tar.gz focaccia-qemu-ef9c5ea85d83459361449259418726a5d4d0a751.zip | |
semihosting: Split is_64bit_semihosting per target
We already have some larger ifdef blocks for ARM and RISCV; split the function into multiple implementations per arch. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'semihosting/arm-compat-semi.c')
| -rw-r--r-- | semihosting/arm-compat-semi.c | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index a9e488886a..d2ce214078 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -213,6 +213,10 @@ common_semi_sys_exit_extended(CPUState *cs, int nr) return (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr)); } +static inline bool is_64bit_semihosting(CPUArchState *env) +{ + return is_a64(env); +} #endif /* TARGET_ARM */ #ifdef TARGET_RISCV @@ -238,6 +242,10 @@ common_semi_sys_exit_extended(CPUState *cs, int nr) return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 8); } +static inline bool is_64bit_semihosting(CPUArchState *env) +{ + return riscv_cpu_mxl(env) != MXL_RV32; +} #endif /* @@ -587,17 +595,6 @@ static const GuestFDFunctions guestfd_fns[] = { * call if the memory read fails. Eventually we could use a generic * CPUState helper function here. */ -static inline bool is_64bit_semihosting(CPUArchState *env) -{ -#if defined(TARGET_ARM) - return is_a64(env); -#elif defined(TARGET_RISCV) - return riscv_cpu_mxl(env) != MXL_RV32; -#else -#error un-handled architecture -#endif -} - #define GET_ARG(n) do { \ if (is_64bit_semihosting(env)) { \ |