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authorAnthony Liguori <aliguori@us.ibm.com>2012-08-11 19:49:03 -0500
committerAnthony Liguori <aliguori@us.ibm.com>2012-08-11 19:49:03 -0500
commit346fe0c4c0b88f11a3d0c01c34d9a170d73429cc (patch)
tree699be308892b0a9c1f31d8025c092a99f3418b00 /target-arm/cpu.h
parent53810bab3acd73b9844807e53f02d867c1ad1d2a (diff)
parentb90372ad2a69a9cdad2a40766eb46f0a89d98535 (diff)
downloadfocaccia-qemu-346fe0c4c0b88f11a3d0c01c34d9a170d73429cc.tar.gz
focaccia-qemu-346fe0c4c0b88f11a3d0c01c34d9a170d73429cc.zip
Merge remote-tracking branch 'stefanha/trivial-patches' into staging
* stefanha/trivial-patches:
  target-arm: Fix typos in comments
  arm: translate: comment typo - s/middel/middle/
  vl.c: Exit QEMU early if no machine is found
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r--target-arm/cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 191895cca8..d7f93d98f0 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -79,7 +79,7 @@ struct arm_boot_info;
 typedef struct CPUARMState {
     /* Regs for current mode.  */
     uint32_t regs[16];
-    /* Frequently accessed CPSR bits are stored separately for efficiently.
+    /* Frequently accessed CPSR bits are stored separately for efficiency.
        This contains all the other bits.  Use cpsr_{read,write} to access
        the whole CPSR.  */
     uint32_t uncached_cpsr;