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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-06-14 16:04:25 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-06-14 16:04:25 +0100 |
| commit | 1be08a0946b1a189ac72822182c37367e8cd3d87 (patch) | |
| tree | 2c41b2e3abf67957ea1b75e7d5330ab2b1dff4fe /target-arm/helper.c | |
| parent | 7474f1be701f136b224af5e1abe55e97dc3f29a5 (diff) | |
| parent | fe8fcf3d642b4de1369841bf6acac13e0ec8770d (diff) | |
| download | focaccia-qemu-1be08a0946b1a189ac72822182c37367e8cd3d87.tar.gz focaccia-qemu-1be08a0946b1a189ac72822182c37367e8cd3d87.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160614-2' into staging
target-arm queue: * add PMU support for virt machine under KVM * fix reset and migration of TTBCR(S) * add virt-2.7 machine type * QOMify various ARM devices * implement xilinx DisplayPort device * don't permit ARMv8-only Neon insns to work on ARMv7 # gpg: Signature made Tue 14 Jun 2016 16:01:45 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20160614-2: (30 commits) target-arm: Don't permit ARMv8-only Neon insns on ARMv7 arm: xlnx-zynqmp: Add xlnx-dp and xlnx-dpdma introduce xlnx-dp introduce xlnx-dpdma hw/i2c-ddc.c: Implement DDC I2C slave introduce dpcd module introduce aux-bus i2c: Factor our send() and recv() common logic i2c: implement broadcast write i2cbus: remove unused dev field hw/sd: QOM'ify pl181.c hw/dma: QOM'ify pxa2xx_dma.c hw/misc: QOM'ify mst_fpga.c hw/misc: QOM'ify exynos4210_pmu.c hw/misc: QOM'ify arm_l2x0.c hw/gpio: QOM'ify zaurus.c hw/gpio: QOM'ify pl061.c hw/gpio: QOM'ify omap_gpio.c hw/i2c: QOM'ify versatile_i2c.c hw/i2c: QOM'ify omap_i2c.c ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/helper.c')
| -rw-r--r-- | target-arm/helper.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index 862e7808a2..c9730d6678 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3765,8 +3765,11 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, .access = PL3_RW, /* no .writefn needed as this can't cause an ASID change; - * no .raw_writefn or .resetfn needed as we never use mask/base_mask + * we must provide a .raw_writefn and .resetfn because we handle + * reset and migration for the AArch32 TTBCR(S), which might be + * using mask and base_mask. */ + .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, |