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| author | Lars Munch <lars@segv.dk> | 2010-05-08 22:43:35 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-05-31 19:40:41 +0200 |
| commit | e03c22a98cf5deffd0dec2f9ff88a600aa330bc4 (patch) | |
| tree | dbb06162b962ef194e422e40641d559b31087662 /target-arm/helper.c | |
| parent | 0f89cc7b6c33418f268126cc908b222e0d052f69 (diff) | |
| download | focaccia-qemu-e03c22a98cf5deffd0dec2f9ff88a600aa330bc4.tar.gz focaccia-qemu-e03c22a98cf5deffd0dec2f9ff88a600aa330bc4.zip | |
arm: fix arm kernel boot for non zero start addr
Booting an arm kernel has been broken a while when booting from non zero start address. This is due to the order of events: board init loads the kernel and sets register 15 to the start address and then qemu_system_reset reset the cpu making register 15 zero again. This patch fixes the usage of the register 15 start address trick in combination with arm_load_kernel. Signed-off-by: Lars Munch <lars@segv.dk> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-arm/helper.c')
| -rw-r--r-- | target-arm/helper.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index 99e0394e93..63e5dc7ef6 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -207,7 +207,6 @@ void cpu_reset(CPUARMState *env) #else /* SVC mode with interrupts disabled. */ env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; - env->regs[15] = 0; /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is clear at reset. Initial SP and PC are loaded from ROM. */ if (IS_M(env)) { |