diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2016-09-06 13:33:17 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-09-06 13:33:17 +0100 |
| commit | 085c9150195b383cb978351e12d24df9ba129ae9 (patch) | |
| tree | 39569dd54ded58068aae78957dccc913ca077782 /target-i386/cpu.h | |
| parent | 30e7d092b26146eb2abb77e0a0952aea012e36bf (diff) | |
| parent | 6546d0dba6c211c1a3eac1252a4f50a0c151a08a (diff) | |
| download | focaccia-qemu-085c9150195b383cb978351e12d24df9ba129ae9.tar.gz focaccia-qemu-085c9150195b383cb978351e12d24df9ba129ae9.zip | |
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging
x86 and memory backends queue, 2016-09-05 This includes a few features that were submitted just after hard freeze, and a bug fix for memory backend initialization ordering. # gpg: Signature made Mon 05 Sep 2016 20:50:14 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-pull-request: vl: Delay initialization of memory backends vhost-user-test: Use libqos instead of pxe-virtio.rom target-i386: Add more Intel AVX-512 instructions support exec: Ensure the only one cpu_index allocation method is used Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-i386/cpu.h')
| -rw-r--r-- | target-i386/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 65615c0f3b..cf14bcb6d0 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -606,16 +606,21 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EBX_RTM (1U << 11) #define CPUID_7_0_EBX_MPX (1U << 14) #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */ +#define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */ #define CPUID_7_0_EBX_RDSEED (1U << 18) #define CPUID_7_0_EBX_ADX (1U << 19) #define CPUID_7_0_EBX_SMAP (1U << 20) +#define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */ #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */ #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ +#define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */ +#define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */ +#define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */ #define CPUID_7_0_ECX_UMIP (1U << 2) #define CPUID_7_0_ECX_PKU (1U << 3) #define CPUID_7_0_ECX_OSPKE (1U << 4) |