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authorMichael Walle <michael@walle.cc>2013-09-18 19:10:45 +0200
committerMichael Walle <michael@walle.cc>2014-02-04 19:47:06 +0100
commit3dd3a2b965a2d2f5b9c53ab86194b78a546a8fc5 (patch)
treeefb294ea9457149f57eb3ab5f298ef7d690ea7d2 /target-lm32/cpu.h
parent34f4aa83f96722aa2c36fbe179108863ebe6e3e9 (diff)
downloadfocaccia-qemu-3dd3a2b965a2d2f5b9c53ab86194b78a546a8fc5.tar.gz
focaccia-qemu-3dd3a2b965a2d2f5b9c53ab86194b78a546a8fc5.zip
target-lm32: add breakpoint/watchpoint support
This patch adds in-target breakpoint and watchpoint support.

Signed-off-by: Michael Walle <michael@walle.cc>
Diffstat (limited to 'target-lm32/cpu.h')
-rw-r--r--target-lm32/cpu.h27
1 files changed, 25 insertions, 2 deletions
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index 101df8045c..18cf3488f7 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -163,8 +163,11 @@ struct CPULM32State {
 
     /* debug registers */
     uint32_t dc;        /* debug control */
-    uint32_t bp[4];     /* breakpoint addresses */
-    uint32_t wp[4];     /* watchpoint addresses */
+    uint32_t bp[4];     /* breakpoints */
+    uint32_t wp[4];     /* watchpoints */
+
+    CPUBreakpoint * cpu_breakpoint[4];
+    CPUWatchpoint * cpu_watchpoint[4];
 
     CPU_COMMON
 
@@ -181,6 +184,19 @@ struct CPULM32State {
 
 };
 
+typedef enum {
+    LM32_WP_DISABLED = 0,
+    LM32_WP_READ,
+    LM32_WP_WRITE,
+    LM32_WP_READ_WRITE,
+} lm32_wp_t;
+
+static inline lm32_wp_t lm32_wp_type(uint32_t dc, int idx)
+{
+    assert(idx < 4);
+    return (dc >> (idx+1)*2) & 0x3;
+}
+
 #include "cpu-qom.h"
 
 LM32CPU *cpu_lm32_init(const char *cpu_model);
@@ -193,6 +209,13 @@ int cpu_lm32_signal_handler(int host_signum, void *pinfo,
 void lm32_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 void lm32_translate_init(void);
 void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value);
+void QEMU_NORETURN raise_exception(CPULM32State *env, int index);
+void lm32_debug_excp_handler(CPULM32State *env);
+void lm32_breakpoint_insert(CPULM32State *env, int index, target_ulong address);
+void lm32_breakpoint_remove(CPULM32State *env, int index);
+void lm32_watchpoint_insert(CPULM32State *env, int index, target_ulong address,
+        lm32_wp_t wp_type);
+void lm32_watchpoint_remove(CPULM32State *env, int index);
 
 static inline CPULM32State *cpu_init(const char *cpu_model)
 {