diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2016-02-26 12:54:22 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-02-26 12:54:22 +0000 |
| commit | 4d1e324b2241017c92d816ec3af51a14685dbf62 (patch) | |
| tree | a6a049570bd94df09d5a18bbbdef20ee9883963b /target-mips/cpu.c | |
| parent | a88a5cd2e8b917e76b171e5859bdd2c569fa87ff (diff) | |
| parent | 01bc435b44b8802cc4697faa07d908684afbce4e (diff) | |
| download | focaccia-qemu-4d1e324b2241017c92d816ec3af51a14685dbf62.tar.gz focaccia-qemu-4d1e324b2241017c92d816ec3af51a14685dbf62.zip | |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160226' into staging
MIPS patches 2016-02-26 Changes: * support for FPU and MSA in KVM guest * support for R6 Virtual Processors # gpg: Signature made Fri 26 Feb 2016 11:07:37 GMT using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" * remotes/lalrae/tags/mips-20160226: target-mips: implement R6 multi-threading mips/kvm: Support MSA in MIPS KVM guests mips/kvm: Support FPU in MIPS KVM guests mips/kvm: Support signed 64-bit KVM registers mips/kvm: Support unsigned KVM registers mips/kvm: Implement Config CP0 registers mips/kvm: Implement PRid CP0 register mips/kvm: Remove a couple of noisy DPRINTFs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-mips/cpu.c')
| -rw-r--r-- | target-mips/cpu.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target-mips/cpu.c b/target-mips/cpu.c index 0b3f130cf2..7dc3a44a15 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -77,6 +77,15 @@ static bool mips_cpu_has_work(CPUState *cs) has_work = false; } } + /* MIPS Release 6 has the ability to halt the CPU. */ + if (env->CP0_Config5 & (1 << CP0C5_VP)) { + if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { + has_work = true; + } + if (!mips_vp_active(env)) { + has_work = false; + } + } return has_work; } |