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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-02-15 15:07:00 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-15 15:07:00 +0000 |
| commit | a50f98b0665289fd37720f287943e86f23b01f45 (patch) | |
| tree | c0878c80c5a6a7900056d4fa6a4869a8065b5f29 /target-mips/cpu.h | |
| parent | 933b19ea9784de7ed2eb6e10262b9363c5c03ed7 (diff) | |
| parent | 736d120af4bf5f3e13b2f90c464b3a24847f78f0 (diff) | |
| download | focaccia-qemu-a50f98b0665289fd37720f287943e86f23b01f45.tar.gz focaccia-qemu-a50f98b0665289fd37720f287943e86f23b01f45.zip | |
Merge remote-tracking branch 'remotes/jovanovic/mips-ufrp' into staging
* remotes/jovanovic/mips-ufrp: target-mips: add user-mode FR switch support for MIPS32r5 target-mips: add support for CP0_Config5 target-mips: add support for CP0_Config4 target-mips: add CPU definition for MIPS32R5 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 9caf4474b9..60c80617a5 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -73,6 +73,7 @@ struct CPUMIPSFPUContext { float_status fp_status; /* fpu implementation/revision register (fir) */ uint32_t fcr0; +#define FCR0_UFRP 28 #define FCR0_F64 22 #define FCR0_L 21 #define FCR0_W 20 @@ -368,6 +369,18 @@ struct CPUMIPSState { #define CP0C3_MT 2 #define CP0C3_SM 1 #define CP0C3_TL 0 + uint32_t CP0_Config4; + uint32_t CP0_Config4_rw_bitmask; +#define CP0C4_M 31 + uint32_t CP0_Config5; + uint32_t CP0_Config5_rw_bitmask; +#define CP0C5_M 31 +#define CP0C5_K 30 +#define CP0C5_CV 29 +#define CP0C5_EVA 28 +#define CP0C5_MSAEn 27 +#define CP0C5_UFR 2 +#define CP0C5_NFExists 0 int32_t CP0_Config6; int32_t CP0_Config7; /* XXX: Maybe make LLAddr per-TC? */ |