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| author | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-17 14:53:06 +0000 |
|---|---|---|
| committer | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-17 14:53:06 +0000 |
| commit | 5747c0733dd7ebbaa7a719d5cb1cd22565cb0cb0 (patch) | |
| tree | ac46f19d2183cb0318e6de56c125fc47cd270fa6 /target-mips/fop_template.c | |
| parent | 02ce600c1e485a7da4a26166b5a75b68c6013fe1 (diff) | |
| download | focaccia-qemu-5747c0733dd7ebbaa7a719d5cb1cd22565cb0cb0.tar.gz focaccia-qemu-5747c0733dd7ebbaa7a719d5cb1cd22565cb0cb0.zip | |
Fix int/float inconsistencies.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3672 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/fop_template.c')
| -rw-r--r-- | target-mips/fop_template.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/target-mips/fop_template.c b/target-mips/fop_template.c index 8ee0525130..c5941d1216 100644 --- a/target-mips/fop_template.c +++ b/target-mips/fop_template.c @@ -24,14 +24,14 @@ #define OP_WLOAD_FREG(treg, tregname, FREG) \ void glue(glue(op_load_fpr_,tregname), FREG) (void) \ { \ - treg = env->fpu->fpr[FREG].fs[FP_ENDIAN_IDX]; \ + treg = env->fpu->fpr[FREG].w[FP_ENDIAN_IDX]; \ FORCE_RET(); \ } #define OP_WSTORE_FREG(treg, tregname, FREG) \ void glue(glue(op_store_fpr_,tregname), FREG) (void) \ { \ - env->fpu->fpr[FREG].fs[FP_ENDIAN_IDX] = treg; \ + env->fpu->fpr[FREG].w[FP_ENDIAN_IDX] = treg; \ FORCE_RET(); \ } @@ -50,10 +50,10 @@ OP_WSTORE_FREG(WT2, WT2_fpr, FREG) void glue(glue(op_load_fpr_,tregname), FREG) (void) \ { \ if (env->hflags & MIPS_HFLAG_F64) \ - treg = env->fpu->fpr[FREG].fd; \ + treg = env->fpu->fpr[FREG].d; \ else \ - treg = (uint64_t)(env->fpu->fpr[FREG | 1].fs[FP_ENDIAN_IDX]) << 32 | \ - env->fpu->fpr[FREG & ~1].fs[FP_ENDIAN_IDX]; \ + treg = (uint64_t)(env->fpu->fpr[FREG | 1].w[FP_ENDIAN_IDX]) << 32 | \ + env->fpu->fpr[FREG & ~1].w[FP_ENDIAN_IDX]; \ FORCE_RET(); \ } @@ -61,10 +61,10 @@ OP_WSTORE_FREG(WT2, WT2_fpr, FREG) void glue(glue(op_store_fpr_,tregname), FREG) (void) \ { \ if (env->hflags & MIPS_HFLAG_F64) \ - env->fpu->fpr[FREG].fd = treg; \ + env->fpu->fpr[FREG].d = treg; \ else { \ - env->fpu->fpr[FREG | 1].fs[FP_ENDIAN_IDX] = treg >> 32; \ - env->fpu->fpr[FREG & ~1].fs[FP_ENDIAN_IDX] = treg; \ + env->fpu->fpr[FREG | 1].w[FP_ENDIAN_IDX] = treg >> 32; \ + env->fpu->fpr[FREG & ~1].w[FP_ENDIAN_IDX] = treg; \ } \ FORCE_RET(); \ } @@ -81,14 +81,14 @@ OP_DSTORE_FREG(DT2, DT2_fpr, FREG) #define OP_PSLOAD_FREG(treg, tregname, FREG) \ void glue(glue(op_load_fpr_,tregname), FREG) (void) \ { \ - treg = env->fpu->fpr[FREG].fs[!FP_ENDIAN_IDX]; \ + treg = env->fpu->fpr[FREG].w[!FP_ENDIAN_IDX]; \ FORCE_RET(); \ } #define OP_PSSTORE_FREG(treg, tregname, FREG) \ void glue(glue(op_store_fpr_,tregname), FREG) (void) \ { \ - env->fpu->fpr[FREG].fs[!FP_ENDIAN_IDX] = treg; \ + env->fpu->fpr[FREG].w[!FP_ENDIAN_IDX] = treg; \ FORCE_RET(); \ } |