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authorAndreas Färber <afaerber@suse.de>2013-07-07 13:05:05 +0200
committerAndreas Färber <afaerber@suse.de>2013-07-27 00:04:17 +0200
commit986a2998932e978e63fc3b7ead1fef81f7aad52e (patch)
tree93d84a9f6c46c1bd4a9d98d9c9463ed276ca4260 /target-mips/gdbstub.c
parent25d8ac0e31c3c68dfdd6da7c33b87870b4a3b623 (diff)
downloadfocaccia-qemu-986a2998932e978e63fc3b7ead1fef81f7aad52e.tar.gz
focaccia-qemu-986a2998932e978e63fc3b7ead1fef81f7aad52e.zip
gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functions
This avoids polluting the global namespace with a non-prefixed macro and
makes it obvious in the call sites that we return.

Semi-automatic conversion using, e.g.,
 sed -i 's/GET_REGL(/return gdb_get_regl(mem_buf, /g' target-*/gdbstub.c
followed by manual tweaking for sparc's GET_REGA() and Coding Style.

Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-mips/gdbstub.c')
-rw-r--r--target-mips/gdbstub.c31
1 files changed, 17 insertions, 14 deletions
diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c
index 15dc281ea5..db826d8516 100644
--- a/target-mips/gdbstub.c
+++ b/target-mips/gdbstub.c
@@ -21,44 +21,47 @@
 static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
 {
     if (n < 32) {
-        GET_REGL(env->active_tc.gpr[n]);
+        return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
     }
     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
         if (n >= 38 && n < 70) {
             if (env->CP0_Status & (1 << CP0St_FR)) {
-                GET_REGL(env->active_fpu.fpr[n - 38].d);
+                return gdb_get_regl(mem_buf,
+                    env->active_fpu.fpr[n - 38].d);
             } else {
-                GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
+                return gdb_get_regl(mem_buf,
+                    env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
             }
         }
         switch (n) {
         case 70:
-            GET_REGL((int32_t)env->active_fpu.fcr31);
+            return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31);
         case 71:
-            GET_REGL((int32_t)env->active_fpu.fcr0);
+            return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
         }
     }
     switch (n) {
     case 32:
-        GET_REGL((int32_t)env->CP0_Status);
+        return gdb_get_regl(mem_buf, (int32_t)env->CP0_Status);
     case 33:
-        GET_REGL(env->active_tc.LO[0]);
+        return gdb_get_regl(mem_buf, env->active_tc.LO[0]);
     case 34:
-        GET_REGL(env->active_tc.HI[0]);
+        return gdb_get_regl(mem_buf, env->active_tc.HI[0]);
     case 35:
-        GET_REGL(env->CP0_BadVAddr);
+        return gdb_get_regl(mem_buf, env->CP0_BadVAddr);
     case 36:
-        GET_REGL((int32_t)env->CP0_Cause);
+        return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause);
     case 37:
-        GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
+        return gdb_get_regl(mem_buf, env->active_tc.PC |
+                                     !!(env->hflags & MIPS_HFLAG_M16));
     case 72:
-        GET_REGL(0); /* fp */
+        return gdb_get_regl(mem_buf, 0); /* fp */
     case 89:
-        GET_REGL((int32_t)env->CP0_PRid);
+        return gdb_get_regl(mem_buf, (int32_t)env->CP0_PRid);
     }
     if (n >= 73 && n <= 88) {
         /* 16 embedded regs.  */
-        GET_REGL(0);
+        return gdb_get_regl(mem_buf, 0);
     }
 
     return 0;