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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-10-30 16:30:25 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-10-30 16:30:25 +0000 |
| commit | e79ea9e4240971b43494184d68a7f5a67d07e74b (patch) | |
| tree | 61cb35e3af977e54626c32038895d0f02e520cad /target-mips/helper.c | |
| parent | fdf927621a99711bf1a81712bce054794f2d44c3 (diff) | |
| parent | 60270f85cc93d2d34e45b7679c374b1d771f0eeb (diff) | |
| download | focaccia-qemu-e79ea9e4240971b43494184d68a7f5a67d07e74b.tar.gz focaccia-qemu-e79ea9e4240971b43494184d68a7f5a67d07e74b.zip | |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20151030' into staging
MIPS patches 2015-10-30 Changes: * R6 CPU can be woken up by non-enabled interrupts * PC fix in KVM * Coprocessor 0 XContext calculation fix * various MIPS R6 updates # gpg: Signature made Fri 30 Oct 2015 14:51:56 GMT using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" * remotes/lalrae/tags/mips-20151030: target-mips: fix updating XContext on mmu exception target-mips: add SIGRIE instruction target-mips: Set Config5.XNP for R6 cores target-mips: add PC, XNP reg numbers to RDHWR hw/mips_malta: Fix KVM PC initialisation target-mips: Add enum for BREAK32 target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6 target-mips: implement the CPU wake-up on non-enabled interrupts in R6 target-mips: move the test for enabled interrupts to a separate function Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-mips/helper.c')
| -rw-r--r-- | target-mips/helper.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/target-mips/helper.c b/target-mips/helper.c index 01c4461573..b3fe816fec 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -293,9 +293,10 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); #if defined(TARGET_MIPS64) env->CP0_EntryHi &= env->SEGMask; - env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | - ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) | - ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); + env->CP0_XContext = + /* PTEBase */ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | + /* R */ (extract64(address, 62, 2) << (env->SEGBITS - 9)) | + /* BadVPN2 */ (extract64(address, 13, env->SEGBITS - 13) << 4); #endif cs->exception_index = exception; env->error_code = error_code; @@ -759,7 +760,8 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; - if (cpu_mips_hw_interrupts_pending(env)) { + if (cpu_mips_hw_interrupts_enabled(env) && + cpu_mips_hw_interrupts_pending(env)) { /* Raise it */ cs->exception_index = EXCP_EXT_INTERRUPT; env->error_code = 0; |