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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-02-15 15:07:00 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-15 15:07:00 +0000 |
| commit | a50f98b0665289fd37720f287943e86f23b01f45 (patch) | |
| tree | c0878c80c5a6a7900056d4fa6a4869a8065b5f29 /target-mips/mips-defs.h | |
| parent | 933b19ea9784de7ed2eb6e10262b9363c5c03ed7 (diff) | |
| parent | 736d120af4bf5f3e13b2f90c464b3a24847f78f0 (diff) | |
| download | focaccia-qemu-a50f98b0665289fd37720f287943e86f23b01f45.tar.gz focaccia-qemu-a50f98b0665289fd37720f287943e86f23b01f45.zip | |
Merge remote-tracking branch 'remotes/jovanovic/mips-ufrp' into staging
* remotes/jovanovic/mips-ufrp: target-mips: add user-mode FR switch support for MIPS32r5 target-mips: add support for CP0_Config5 target-mips: add support for CP0_Config4 target-mips: add CPU definition for MIPS32R5 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-mips/mips-defs.h')
| -rw-r--r-- | target-mips/mips-defs.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index bf094a3bd5..9dfa5168da 100644 --- a/target-mips/mips-defs.h +++ b/target-mips/mips-defs.h @@ -29,6 +29,8 @@ #define ISA_MIPS32R2 0x00000040 #define ISA_MIPS64 0x00000080 #define ISA_MIPS64R2 0x00000100 +#define ISA_MIPS32R3 0x00000200 +#define ISA_MIPS32R5 0x00000400 /* MIPS ASEs. */ #define ASE_MIPS16 0x00001000 @@ -64,6 +66,12 @@ #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) +/* MIPS Technologies "Release 3" */ +#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) + +/* MIPS Technologies "Release 5" */ +#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) + /* Strictly follow the architecture standard: - Disallow "special" instruction handling for PMON/SPIM. Note that we still maintain Count/Compare to match the host clock. */ |