diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2015-07-16 10:40:22 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-07-16 10:40:23 +0100 |
| commit | 2d5ee9e7a7dd495d233cf9613a865f63f88e3375 (patch) | |
| tree | 3cf2c0776c76a23a1fd546535b63abd5a285c24b /target-mips/msa_helper.c | |
| parent | 3749c11a720689694101dcf2ebc43217a02f960f (diff) | |
| parent | 908680c6441ac468f4871d513f42be396ea0d264 (diff) | |
| download | focaccia-qemu-2d5ee9e7a7dd495d233cf9613a865f63f88e3375.tar.gz focaccia-qemu-2d5ee9e7a7dd495d233cf9613a865f63f88e3375.zip | |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150716' into staging
MIPS patches 2015-07-16 Changes: * bug fixes # gpg: Signature made Thu Jul 16 09:04:56 2015 BST using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B * remotes/lalrae/tags/mips-20150716: target-mips: fix page fault address for LWL/LWR/LDL/LDR linux-user: Fix MIPS N64 trap and break instruction bug target-mips: fix resource leak reported by Coverity target-mips: fix logically dead code reported by Coverity target-mips: correct DERET instruction target-mips: fix ASID synchronisation for MIPS MT disas/mips: fix disassembling R6 instructions target-mips: fix to clear MSACSR.Cause target-mips: fix MIPS64R6-generic configuration Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-mips/msa_helper.c')
| -rw-r--r-- | target-mips/msa_helper.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target-mips/msa_helper.c b/target-mips/msa_helper.c index 26ffdc726e..a1cb48f2a9 100644 --- a/target-mips/msa_helper.c +++ b/target-mips/msa_helper.c @@ -2642,6 +2642,8 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwt = &(env->active_fpu.fpr[wt].wr); uint32_t i; + clear_msacsr_cause(env); + switch (df) { case DF_WORD: for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { @@ -3192,6 +3194,8 @@ void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pws = &(env->active_fpu.fpr[ws].wr); uint32_t i; + clear_msacsr_cause(env); + switch (df) { case DF_WORD: for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { @@ -3224,6 +3228,8 @@ void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pws = &(env->active_fpu.fpr[ws].wr); uint32_t i; + clear_msacsr_cause(env); + switch (df) { case DF_WORD: for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |