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authorAndreas Färber <afaerber@suse.de>2012-12-17 19:47:15 +0100
committerAndreas Färber <afaerber@suse.de>2013-01-15 04:09:14 +0100
commit38d8f5c84e7c02f2523005dddc31939ca18232dd (patch)
treeb331156b39565092fe7f860647b912730367ffcd /target-mips/op_helper.c
parent4a1e40b5091bcff5f8ea3fe9963eaa8e76b16389 (diff)
downloadfocaccia-qemu-38d8f5c84e7c02f2523005dddc31939ca18232dd.tar.gz
focaccia-qemu-38d8f5c84e7c02f2523005dddc31939ca18232dd.zip
exec: Return CPUState from qemu_get_cpu()
Move the declaration to qemu/cpu.h and add documentation.
The implementation still depends on CPUArchState for CPU iteration.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-mips/op_helper.c')
-rw-r--r--target-mips/op_helper.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 1816a0ec8d..1bca4a159e 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -585,8 +585,9 @@ static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
           walking the list of CPUMIPSStates.  */
 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 {
+    MIPSCPU *cpu;
     CPUState *cs;
-    CPUMIPSState *other;
+    CPUState *other_cs;
     int vpe_idx;
     int tc_idx = *tc;
 
@@ -599,8 +600,12 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
     cs = CPU(mips_env_get_cpu(env));
     vpe_idx = tc_idx / cs->nr_threads;
     *tc = tc_idx % cs->nr_threads;
-    other = qemu_get_cpu(vpe_idx);
-    return other ? other : env;
+    other_cs = qemu_get_cpu(vpe_idx);
+    if (other_cs == NULL) {
+        return env;
+    }
+    cpu = MIPS_CPU(other_cs);
+    return &cpu->env;
 }
 
 /* The per VPE CP0_Status register shares some fields with the per TC