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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-07-16 10:40:22 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-07-16 10:40:23 +0100 |
| commit | 2d5ee9e7a7dd495d233cf9613a865f63f88e3375 (patch) | |
| tree | 3cf2c0776c76a23a1fd546535b63abd5a285c24b /target-mips/translate_init.c | |
| parent | 3749c11a720689694101dcf2ebc43217a02f960f (diff) | |
| parent | 908680c6441ac468f4871d513f42be396ea0d264 (diff) | |
| download | focaccia-qemu-2d5ee9e7a7dd495d233cf9613a865f63f88e3375.tar.gz focaccia-qemu-2d5ee9e7a7dd495d233cf9613a865f63f88e3375.zip | |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150716' into staging
MIPS patches 2015-07-16 Changes: * bug fixes # gpg: Signature made Thu Jul 16 09:04:56 2015 BST using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B * remotes/lalrae/tags/mips-20150716: target-mips: fix page fault address for LWL/LWR/LDL/LDR linux-user: Fix MIPS N64 trap and break instruction bug target-mips: fix resource leak reported by Coverity target-mips: fix logically dead code reported by Coverity target-mips: correct DERET instruction target-mips: fix ASID synchronisation for MIPS MT disas/mips: fix disassembling R6 instructions target-mips: fix to clear MSACSR.Cause target-mips: fix MIPS64R6-generic configuration Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index ddfaff8052..9304e746b4 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -655,14 +655,14 @@ static const mips_def_t mips_defs[] = (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) | - (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1 << CP0C3_LPA) | - (1U << CP0C3_M), - .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | - (3 << CP0C4_IE) | (1 << CP0C4_M), + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | + (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | + (1 << CP0C3_RXI) | (1 << CP0C3_LPA), + .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | + (0xfc << CP0C4_KScrExist), .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_LLB), - .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | - (1 << CP0C5_UFE), + .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | + (1 << CP0C5_FRE) | (1 << CP0C5_UFE), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 0, .SYNCI_Step = 32, @@ -674,9 +674,9 @@ static const mips_def_t mips_defs[] = .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), - .SEGBITS = 42, + .SEGBITS = 48, .PABITS = 48, - .insn_flags = CPU_MIPS64R6, + .insn_flags = CPU_MIPS64R6 | ASE_MSA, .mmu_type = MMU_TYPE_R4000, }, { |