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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-11-10 13:56:47 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-11-10 13:56:47 +0000 |
| commit | 2d9177588bde9881c6602284d1b0b08e4dfe361e (patch) | |
| tree | 047fad0a24365ed125454953746daa7a4b88ca67 /target-mips/translate_init.c | |
| parent | 7b4b7c5fc7f25a161839802ca7d23f50f99e5174 (diff) | |
| parent | cb269f273fdbdb26ddb1cba4a0fe2249418a8e77 (diff) | |
| download | focaccia-qemu-2d9177588bde9881c6602284d1b0b08e4dfe361e.tar.gz focaccia-qemu-2d9177588bde9881c6602284d1b0b08e4dfe361e.zip | |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20141107' into staging
* remotes/lalrae/tags/mips-20141107: target-mips: fix multiple TCG registers covering same data mips: Ensure PC update with MTC0 single-stepping target-mips: fix for missing delay slot in BC1EQZ and BC1NEZ mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits mips: Add macros for CP0.Config3 and CP0.Config4 bits mips: Respect CP0.Status.CU1 for microMIPS FP branches mips: Remove CONFIG_VT82C686 from non-Fulong configs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 4dee1caf92..148b394cf0 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -333,7 +333,8 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP), + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | + (0 << CP0C3_VInt), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, @@ -376,7 +377,7 @@ static const mips_def_t mips_defs[] = (0x93 << FCR0_PRID), .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2 | ASE_MSA, + .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA, .mmu_type = MMU_TYPE_R4000, }, #if defined(TARGET_MIPS64) @@ -601,7 +602,8 @@ static const mips_def_t mips_defs[] = (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) | + (1 << CP0C3_DSPP) | (1 << CP0C3_LPA), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 0, .SYNCI_Step = 32, |