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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-09-23 15:28:07 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-09-23 15:28:07 +0100 |
| commit | eaff9c4367ac3f7ac44f6c6f4cb7bcd4daa89af5 (patch) | |
| tree | 1c9ac2b900ee4a373c81ac7c6f9b512cd5018c77 /target-mips/translate_init.c | |
| parent | c229472af095765cdbae95ad057b170d98f81e25 (diff) | |
| parent | fea55615b2f924128e115ceb2265069561b03ef8 (diff) | |
| download | focaccia-qemu-eaff9c4367ac3f7ac44f6c6f4cb7bcd4daa89af5.tar.gz focaccia-qemu-eaff9c4367ac3f7ac44f6c6f4cb7bcd4daa89af5.zip | |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160923' into staging
MIPS patches 2016-09-23 Changes: * 24KEc CPU definition * SYNC instructions make use of tcg memory barrier ops * various MIPS linux-user bug fixes # gpg: Signature made Fri 23 Sep 2016 08:09:08 BST # gpg: using RSA key 0x52118E3C0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" # Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B * remotes/lalrae/tags/mips-20160923: linux-user: Add missing Mips syscalls items in strace.list linux-user: Add missing TARGET_EDQUOT error code for Mips linux-user: Fix certain argument alignment cases for Mips64 linux-user: Fix structure target_semid64_ds definition for Mips linux-user: Fix structure target_flock definition for Mips linux-user: Fix TARGET_F_GETOWN definition for Mips linux-user: Fix TARGET_SIOCATMARK definition for Mips target-mips: generate fences target-mips: add 24KEc CPU definition Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 39ed5c4c1b..6ae23e476f 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -256,6 +256,28 @@ static const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { + .name = "24KEc", + .CP0_PRid = 0x00019600, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + /* we have a DSP, but no FPU */ + .CP0_Status_rw_bitmask = 0x1378FF1F, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, + .mmu_type = MMU_TYPE_R4000, + }, + { .name = "24Kf", .CP0_PRid = 0x00019300, .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |