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| author | Sebastian Macke <sebastian@macke.de> | 2013-10-22 02:12:37 +0200 |
|---|---|---|
| committer | Jia Liu <proljc@gmail.com> | 2013-11-20 21:40:07 +0800 |
| commit | 352367e8bb53bd4e16abaecbcb9fc0bcadf5881b (patch) | |
| tree | 72023dae654c9d8d74fca9022c35edeb91ce4a22 /target-openrisc/mmu.c | |
| parent | 394cfa39ba24dd838ace1308ae24961243947fb8 (diff) | |
| download | focaccia-qemu-352367e8bb53bd4e16abaecbcb9fc0bcadf5881b.tar.gz focaccia-qemu-352367e8bb53bd4e16abaecbcb9fc0bcadf5881b.zip | |
target-openrisc: Speed up move instruction
The OpenRISC architecture does not have its own move register instruction. Instead it uses either "l.addi rd, r0, x" or "l.ori rd, rs, 0" or "l.or rd, rx, r0" The l.ori instruction is automatically optimized but not the l.addi instruction. This patch optimizes for this special case. Signed-off-by: Sebastian Macke <sebastian@macke.de> Reviewed-by: Jia Liu <proljc@gmail.com> Signed-off-by: Jia Liu <proljc@gmail.com>
Diffstat (limited to 'target-openrisc/mmu.c')
0 files changed, 0 insertions, 0 deletions