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| author | David Gibson <david@gibson.dropbear.id.au> | 2011-04-01 15:15:18 +1100 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2011-04-01 18:34:55 +0200 |
| commit | cdaee00633cfac7338d8dd0ba3e8766d5bdb1cec (patch) | |
| tree | c961c7c035d9a1a3c46b5a18cd0df05793bf89e8 /target-ppc/cpu.h | |
| parent | 256cebe5d17477cd1443f47a9bd5ca35ca0dbc9c (diff) | |
| download | focaccia-qemu-cdaee00633cfac7338d8dd0ba3e8766d5bdb1cec.tar.gz focaccia-qemu-cdaee00633cfac7338d8dd0ba3e8766d5bdb1cec.zip | |
Support 1T segments on ppc
Traditionally, the "segments" used for the two-stage translation used on powerpc MMUs were 256MB in size. This was the only option on all hash page table based 32-bit powerpc cpus, and on the earlier 64-bit hash page table based cpus. However, newer 64-bit cpus also permit 1TB segments This patch adds support for 1TB segment translation to the qemu code. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index fd2dfcd92c..10341b307f 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -114,6 +114,7 @@ enum powerpc_mmu_t { POWERPC_MMU_601 = 0x0000000A, #if defined(TARGET_PPC64) #define POWERPC_MMU_64 0x00010000 +#define POWERPC_MMU_1TSEG 0x00020000 /* 64 bits PowerPC MMU */ POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, /* 620 variant (no segment exceptions) */ @@ -382,9 +383,11 @@ struct ppc_slb_t { /* Bits in the SLB VSID word */ #define SLB_VSID_SHIFT 12 +#define SLB_VSID_SHIFT_1T 24 #define SLB_VSID_SSIZE_SHIFT 62 #define SLB_VSID_B 0xc000000000000000ULL #define SLB_VSID_B_256M 0x0000000000000000ULL +#define SLB_VSID_B_1T 0x4000000000000000ULL #define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL #define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID) #define SLB_VSID_KS 0x0000000000000800ULL @@ -398,6 +401,10 @@ struct ppc_slb_t { #define SEGMENT_SHIFT_256M 28 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1)) +#define SEGMENT_SHIFT_1T 40 +#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1)) + + /*****************************************************************************/ /* Machine state register bits definition */ #define MSR_SF 63 /* Sixty-four-bit mode hflags */ |