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| author | Paolo Bonzini <pbonzini@redhat.com> | 2013-03-05 15:35:17 +0100 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2014-05-13 13:21:51 +0200 |
| commit | 4a92a558f49cb0693e36bd6d4f9217f298045be2 (patch) | |
| tree | 931ba97c48f579e0c0abe0a45b23a0cecd816879 /target-ppc | |
| parent | 7b4d915e11ae7afb2d42a8cae90db26bc0c142b8 (diff) | |
| download | focaccia-qemu-4a92a558f49cb0693e36bd6d4f9217f298045be2.tar.gz focaccia-qemu-4a92a558f49cb0693e36bd6d4f9217f298045be2.zip | |
cpu: make CPU_INTERRUPT_RESET available on all targets
On the x86, some devices need access to the CPU reset pin (INIT#). Provide a generic service to do this, using one of the internal cpu_interrupt targets. Generalize the PPC-specific code for CPU_INTERRUPT_RESET to other targets. Since PPC does not support migration across QEMU versions (its machine types are not versioned yet), I picked the value that is used on x86, CPU_INTERRUPT_TGT_INT_1. Consequently, TGT_INT_2 and TGT_INT_3 are shifted down by one while keeping their value. Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/cpu.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index d4983405a2..75ed5fa636 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -2042,9 +2042,6 @@ enum { PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */ }; -/* CPU should be reset next, restart from scratch afterwards */ -#define CPU_INTERRUPT_RESET CPU_INTERRUPT_TGT_INT_0 - /*****************************************************************************/ static inline target_ulong cpu_read_xer(CPUPPCState *env) |