summary refs log tree commit diff stats
path: root/target-sparc/cpu.h
diff options
context:
space:
mode:
authorblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2008-08-29 20:50:21 +0000
committerblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2008-08-29 20:50:21 +0000
commit91736d378b9bc6a9d7e16556216c919ba21dc5ca (patch)
treea85752641060c96d1fc88e5b74aeaa090363d9c9 /target-sparc/cpu.h
parenta46256129e80d993d23ed9d95566c79bcfa65e2d (diff)
downloadfocaccia-qemu-91736d378b9bc6a9d7e16556216c919ba21dc5ca.tar.gz
focaccia-qemu-91736d378b9bc6a9d7e16556216c919ba21dc5ca.zip
Fix Sparc64 boot on i386 host:
 - move do_interrupt() back to op_helper.c
 - move non-helper prototypes from helper.h to exec.h
 - move some prototypes from cpu.h to exec.h
 - do not export either set_cwp() or cpu_set_cwp() from op_helper.c,
   but instead provide inline functions


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5109 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc/cpu.h')
-rw-r--r--target-sparc/cpu.h38
1 files changed, 32 insertions, 6 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 8f5e15e438..6006132c8a 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -337,12 +337,17 @@ typedef struct CPUSPARCState {
     } while (0)
 #endif
 
+/* helper.c */
 CPUSPARCState *cpu_sparc_init(const char *cpu_model);
-void gen_intermediate_code_init(CPUSPARCState *env);
-int cpu_sparc_exec(CPUSPARCState *s);
+void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
                                                  ...));
-void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
+
+/* translate.c */
+void gen_intermediate_code_init(CPUSPARCState *env);
+
+/* cpu-exec.c */
+int cpu_sparc_exec(CPUSPARCState *s);
 
 #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) |             \
                       (env->psref? PSR_EF : 0) |                        \
@@ -352,7 +357,29 @@ void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
                       (env->psret? PSR_ET : 0) | env->cwp)
 
 #ifndef NO_CPU_IO_DEFS
-void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
+static inline void memcpy32(target_ulong *dst, const target_ulong *src)
+{
+    dst[0] = src[0];
+    dst[1] = src[1];
+    dst[2] = src[2];
+    dst[3] = src[3];
+    dst[4] = src[4];
+    dst[5] = src[5];
+    dst[6] = src[6];
+    dst[7] = src[7];
+}
+
+static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp)
+{
+    /* put the modified wrap registers at their proper location */
+    if (env1->cwp == env1->nwindows - 1)
+        memcpy32(env1->regbase, env1->regbase + env1->nwindows * 16);
+    env1->cwp = new_cwp;
+    /* put the wrap registers at their temporary location */
+    if (new_cwp == env1->nwindows - 1)
+        memcpy32(env1->regbase + env1->nwindows * 16, env1->regbase);
+    env1->regwptr = env1->regbase + (new_cwp * 16);
+}
 
 static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
 {
@@ -397,10 +424,9 @@ static inline void PUT_CWP64(CPUSPARCState *env1, int cwp)
 #endif
 #endif
 
-int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
+/* cpu-exec.c */
 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
                           int is_asi);
-void cpu_check_irqs(CPUSPARCState *env);
 
 #define CPUState CPUSPARCState
 #define cpu_init cpu_sparc_init