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authorPeter Maydell <peter.maydell@linaro.org>2025-02-01 16:39:56 +0000
committerPeter Maydell <peter.maydell@linaro.org>2025-02-11 16:22:07 +0000
commit0ff5c021f04d7dbaec174451e7a0dab3822b1b0d (patch)
tree019d49228dc730c77d915644a8d5e8679f744275 /target/arm/cpu-features.h
parentd38a57a3f1ea66c4338a10d70c032741e8786c51 (diff)
downloadfocaccia-qemu-0ff5c021f04d7dbaec174451e7a0dab3822b1b0d.tar.gz
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target/arm: Plumb FEAT_RPRES frecpe and frsqrte through to new helper
FEAT_RPRES implements an "increased precision" variant of the single
precision FRECPE and FRSQRTE instructions from an 8 bit to a 12
bit mantissa. This applies only when FPCR.AH == 1. Note that the
halfprec and double versions of these insns retain the 8 bit
precision regardless.

In this commit we add all the plumbing to make these instructions
call a new helper function when the increased-precision is in
effect. In the following commit we will provide the actual change
in behaviour in the helpers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/cpu-features.h')
-rw-r--r--target/arm/cpu-features.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 7bf24c506b..525e4cee12 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -597,6 +597,11 @@ static inline bool isar_feature_aa64_mops(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS);
 }
 
+static inline bool isar_feature_aa64_rpres(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, RPRES);
+}
+
 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
 {
     /* We always set the AdvSIMD and FP fields identically.  */