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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-10-01 09:22:46 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-10-10 14:52:24 +0100 |
| commit | d902ae7558690a8442bf3560d5707167e485ab92 (patch) | |
| tree | 1f8f1914030d23dee47cf796563e41dab77b8f51 /target/arm/cpu-param.h | |
| parent | 7aee3cb9569f83353b17df05dc9d3a7f791b5fdf (diff) | |
| download | focaccia-qemu-d902ae7558690a8442bf3560d5707167e485ab92.tar.gz focaccia-qemu-d902ae7558690a8442bf3560d5707167e485ab92.zip | |
target/arm: Fold secure and non-secure a-profile mmu indexes
For a-profile aarch64, which does not bank system registers, it takes
quite a lot of code to switch between security states. In the process,
registers such as TCR_EL{1,2} must be swapped, which in itself requires
the flushing of softmmu tlbs. Therefore it doesn't buy us anything to
separate tlbs by security state.
Retain the distinction between Stage2 and Stage2_S.
This will be important as we implement FEAT_RME, and do not wish to
add a third set of mmu indexes for Realm state.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu-param.h')
| -rw-r--r-- | target/arm/cpu-param.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 68ffb12427..08681828ac 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -32,6 +32,6 @@ # define TARGET_PAGE_BITS_MIN 10 #endif -#define NB_MMU_MODES 15 +#define NB_MMU_MODES 8 #endif |