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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-07-18 16:29:32 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-07-18 16:29:32 +0100 |
| commit | 782378973121addeb11b13fd12a6ac2e69faa33f (patch) | |
| tree | dbb9f368e6e40347dd41d0a981ac533409e7dae7 /target/arm/cpu.c | |
| parent | 20f55423960ef9f351b49d171c29d257021d75b3 (diff) | |
| parent | 004c8a8bc569c8b18fca6fc90ffe3223daaf17b7 (diff) | |
| download | focaccia-qemu-782378973121addeb11b13fd12a6ac2e69faa33f.tar.gz focaccia-qemu-782378973121addeb11b13fd12a6ac2e69faa33f.zip | |
Merge tag 'pull-target-arm-20220718' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high * target/arm: Fill in VL for tbflags when SME enabled and SVE disabled * target/arm: Fix aarch64_sve_change_el for SME * linux-user/aarch64: Do not clear PROT_MTE on mprotect * target/arm: Honour VTCR_EL2 bits in Secure EL2 * hw/adc: Fix CONV bit in NPCM7XX ADC CON register * hw/adc: Make adci[*] R/W in NPCM7XX ADC * target/arm: Don't set syndrome ISS for loads and stores with writeback * Align Raspberry Pi DMA interrupts with Linux DTS # gpg: Signature made Mon 18 Jul 2022 14:58:26 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20220718' of https://git.linaro.org/people/pmaydell/qemu-arm: Align Raspberry Pi DMA interrupts with Linux DTS target/arm: Don't set syndrome ISS for loads and stores with writeback hw/adc: Make adci[*] R/W in NPCM7XX ADC hw/adc: Fix CONV bit in NPCM7XX ADC CON register target/arm: Honour VTCR_EL2 bits in Secure EL2 target/arm: Store TCR_EL* registers as uint64_t target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_t target/arm: Fix big-endian host handling of VTCR target/arm: Fold regime_tcr() and regime_tcr_value() together target/arm: Calculate mask/base_mask in get_level1_table_address() target/arm: Define and use new regime_tcr_value() function linux-user/aarch64: Do not clear PROT_MTE on mprotect target/arm: Fix aarch64_sve_change_el for SME target/arm: Fill in VL for tbflags when SME enabled and SVE disabled hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.c')
| -rw-r--r-- | target/arm/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5de7e097e9..1b7b3d76bb 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -226,7 +226,7 @@ static void arm_cpu_reset(DeviceState *dev) * Enable TBI0 but not TBI1. * Note that this must match useronly_clean_ptr. */ - env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37); + env->cp15.tcr_el[1] = 5 | (1ULL << 37); /* Enable MTE */ if (cpu_isar_feature(aa64_mte, cpu)) { |