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authorRichard Henderson <richard.henderson@linaro.org>2022-04-17 10:43:35 -0700
committerPeter Maydell <peter.maydell@linaro.org>2022-04-22 14:44:54 +0100
commit063bbd8061bc01b5aee6a9a15db92619bae5418c (patch)
tree12b0b7a1a6df9f69eeae32038d28b2c225c93969 /target/arm/cpu.h
parent2ab370873f62c304898397fdf7da593c43fe6e29 (diff)
downloadfocaccia-qemu-063bbd8061bc01b5aee6a9a15db92619bae5418c.tar.gz
focaccia-qemu-063bbd8061bc01b5aee6a9a15db92619bae5418c.zip
target/arm: Change CPUArchState.thumb to bool
Bool is a more appropriate type for this value.
Adjust the assignments to use true/false.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
-rw-r--r--target/arm/cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 31e4670927..d2a34f6ea8 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -260,6 +260,7 @@ typedef struct CPUArchState {
      */
     uint32_t pstate;
     bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */
+    bool thumb;   /* True if CPU is in thumb mode; cpsr[5] */
 
     /* Cached TBFLAGS state.  See below for which bits are included.  */
     CPUARMTBFlags hflags;
@@ -286,7 +287,6 @@ typedef struct CPUArchState {
     uint32_t ZF; /* Z set if zero.  */
     uint32_t QF; /* 0 or 1 */
     uint32_t GE; /* cpsr[19:16] */
-    uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
     uint32_t btype;  /* BTI branch type.  spsr[11:10].  */
     uint64_t daif; /* exception masks, in the bits they are in PSTATE */