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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-11-02 10:20:25 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-11-02 14:08:38 +0000 |
| commit | 0f8d06f16c9d1041d728d09d464462ebe713c662 (patch) | |
| tree | f105f2424af35a383d977b538d33fd3e0a07d8b6 /target/arm/cpu.h | |
| parent | 5e9fcbd7df8cdddab6566a764cf4e2d4a491fa02 (diff) | |
| download | focaccia-qemu-0f8d06f16c9d1041d728d09d464462ebe713c662.tar.gz focaccia-qemu-0f8d06f16c9d1041d728d09d464462ebe713c662.zip | |
target/arm: Conditionalize some asserts on aarch32 support
When populating id registers from kvm, on a host that doesn't support aarch32 mode at all, neither arm_div nor jazelle will be supported either. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20181102102025.3546-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8e6779936e..b5eff79f73 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3296,6 +3296,11 @@ static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; } +static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; +} + static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; |