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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-03-19 12:46:47 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-04-23 15:07:32 -0700 |
| commit | 21d41c566d0694a90836d5c7ae4c6b279f5312a8 (patch) | |
| tree | acb6d7d0506862211f31d14cc2371a153a8a7aee /target/arm/cpu.h | |
| parent | 79b835f1395ea5cba9a1d5f02c0fb1a429d48e7d (diff) | |
| download | focaccia-qemu-21d41c566d0694a90836d5c7ae4c6b279f5312a8.tar.gz focaccia-qemu-21d41c566d0694a90836d5c7ae4c6b279f5312a8.zip | |
tcg: Declare TARGET_INSN_START_EXTRA_WORDS in 'cpu-param.h'
To avoid including the huge "cpu.h" for a simple definition, move TARGET_INSN_START_EXTRA_WORDS to "cpu-param.h". Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c1a0faed3a..3705b34285 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -98,12 +98,6 @@ #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) #endif -/* ARM-specific extra insn start words: - * 1: Conditional execution bits - * 2: Partial exception syndrome for data aborts - */ -#define TARGET_INSN_START_EXTRA_WORDS 2 - /* The 2nd extra word holding syndrome info for data aborts does not use * the upper 6 bits nor the lower 13 bits. We mask and shift it down to * help the sleb128 encoder do a better job. |