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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-02-07 14:04:22 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-02-07 14:04:22 +0000 |
| commit | 2859d7b590760283a7b5aef40b723e9dfd7c98ba (patch) | |
| tree | bad44adf62e668764c9e0b392b731b752333a3d5 /target/arm/cpu.h | |
| parent | 97fa9350017e647151dd1dc212f1bbca0294dba7 (diff) | |
| download | focaccia-qemu-2859d7b590760283a7b5aef40b723e9dfd7c98ba.tar.gz focaccia-qemu-2859d7b590760283a7b5aef40b723e9dfd7c98ba.zip | |
target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*
This is part of a reorganization to the set of mmu_idx. The EL1&0 regime is the only one that uses 2-stage translation. Spelling out Stage avoids confusion with Secure. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200206105448.4726-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c6da3d3043..afc3e76ce5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2923,8 +2923,8 @@ typedef enum ARMMMUIdx { /* Indexes below here don't have TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. */ - ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, } ARMMMUIdx; /* Bit macros for the core-mmu-index values for each index, |