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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-12-13 13:48:08 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-12-13 14:41:24 +0000 |
| commit | 2d7137c10fafefe40a0a049ff8a7bd78b66e661f (patch) | |
| tree | 1216da5c2346d877845d09b934831eebab22ff38 /target/arm/cpu.h | |
| parent | 7c208e0f4171c9e2cc35efc12e1bf264a45c229f (diff) | |
| download | focaccia-qemu-2d7137c10fafefe40a0a049ff8a7bd78b66e661f.tar.gz focaccia-qemu-2d7137c10fafefe40a0a049ff8a7bd78b66e661f.zip | |
target/arm: Implement the ARMv8.1-LOR extension
Provide a trivial implementation with zero limited ordering regions, which causes the LDLAR and STLLR instructions to devolve into the LDAR and STLR instructions from the base ARMv8.0 instruction set. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181210150501.7990-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 05ac883b6b..c943f35dd9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3340,6 +3340,11 @@ static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; } +static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ |