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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-05-12 16:14:56 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-05-19 16:19:02 +0100 |
| commit | 39f29e599355f9512482b67624e7a6c9000c5ddd (patch) | |
| tree | dd77f822d119d5803f253339394048c47f0a4d46 /target/arm/cpu.h | |
| parent | 84597ff39484ec171567c7c80061100eb4a6c331 (diff) | |
| download | focaccia-qemu-39f29e599355f9512482b67624e7a6c9000c5ddd.tar.gz focaccia-qemu-39f29e599355f9512482b67624e7a6c9000c5ddd.zip | |
hw/intc/arm_gicv3: Use correct number of priority bits for the CPU
Make the GICv3 set its number of bits of physical priority from the implementation-specific value provided in the CPU state struct, in the same way we already do for virtual priority bits. Because this would be a migration compatibility break, we provide a property force-8-bit-prio which is enabled for 7.0 and earlier versioned board models to retain the legacy "always use 8 bits" behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220512151457.3899052-6-peter.maydell@linaro.org Message-id: 20220506162129.2896966-5-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a99b430e54..a42464eb57 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1002,6 +1002,7 @@ struct ArchCPU { int gic_num_lrs; /* number of list registers */ int gic_vpribits; /* number of virtual priority bits */ int gic_vprebits; /* number of virtual preemption bits */ + int gic_pribits; /* number of physical priority bits */ /* Whether the cfgend input is high (i.e. this CPU should reset into * big-endian mode). This setting isn't used directly: instead it modifies |