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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-09-07 13:54:53 +0100 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-09-07 13:54:53 +0100 |
| commit | 62c58ee0b24eafb44c06402fe059fbd7972eb409 (patch) | |
| tree | af7e6106d118cefe157af3c60b3c1be7e92db0cf /target/arm/cpu.h | |
| parent | 4125e6feb71c810ca38f0d8e66e748b472a9cc54 (diff) | |
| download | focaccia-qemu-62c58ee0b24eafb44c06402fe059fbd7972eb409.tar.gz focaccia-qemu-62c58ee0b24eafb44c06402fe059fbd7972eb409.zip | |
target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M
Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security extensions are enabled. We can freely add more items to vmstate_m_security without breaking migration compatibility, because no CPU currently has the ARM_FEATURE_M_SECURITY bit enabled and so this subsection is not yet used by anything. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-14-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 42a6cb2804..d385ef2492 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -543,8 +543,8 @@ typedef struct CPUARMState { * pmsav7.rnr (region number register) * pmsav7_dregion (number of configured regions) */ - uint32_t *rbar; - uint32_t *rlar; + uint32_t *rbar[2]; + uint32_t *rlar[2]; uint32_t mair0[2]; uint32_t mair1[2]; } pmsav8; |