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authorWei Huang <wei@redhat.com>2017-02-10 17:40:28 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-02-10 17:40:28 +0000
commit6b0407805d46bbeba70f4be426285d0a0e669750 (patch)
treee84683292b8e6e72205340367146b41d9802d7a8 /target/arm/cpu.h
parent61eedf7aec0e2395aabd628cc055096909a3ea15 (diff)
downloadfocaccia-qemu-6b0407805d46bbeba70f4be426285d0a0e669750.tar.gz
focaccia-qemu-6b0407805d46bbeba70f4be426285d0a0e669750.zip
target-arm: Add support for PMU register PMSELR_EL0
This patch adds support for AArch64 register PMSELR_EL0. The existing
PMSELR definition is revised accordingly.

Signed-off-by: Wei Huang <wei@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: Moved #ifndef CONFIG_USER_ONLY to cover new regdefs]
Message-id: 1486504171-26807-2-git-send-email-wei@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
-rw-r--r--target/arm/cpu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c0b3832d74..7e609f7a99 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -309,6 +309,7 @@ typedef struct CPUARMState {
         uint32_t c9_pmovsr; /* perf monitor overflow status */
         uint32_t c9_pmxevtyper; /* perf monitor event type */
         uint32_t c9_pmuserenr; /* perf monitor user enable */
+        uint64_t c9_pmselr; /* perf monitor counter selection register */
         uint32_t c9_pminten; /* perf monitor interrupt enables */
         union { /* Memory attribute redirection */
             struct {