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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-02-08 12:58:05 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-02-13 14:14:54 +0000 |
| commit | 70dae0d069c45250bbefd9424089383a8ac239de (patch) | |
| tree | ce6350aeda2e60baad4cefaaf26fce9fe6421b13 /target/arm/cpu.h | |
| parent | d203cabd1bd12f31c9df0b5737421ba67b96857b (diff) | |
| download | focaccia-qemu-70dae0d069c45250bbefd9424089383a8ac239de.tar.gz focaccia-qemu-70dae0d069c45250bbefd9424089383a8ac239de.zip | |
target/arm: Remove CPSR_RESERVED
The only remaining use was in op_helper.c. Use PSTATE_SS directly, and move the commentary so that it is more obvious what is going on. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200208125816.14954-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 694b074298..c6dff1d55b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1186,12 +1186,6 @@ void pmu_init(ARMCPU *cpu); #define CPSR_IT_2_7 (0xfc00U) #define CPSR_GE (0xfU << 16) #define CPSR_IL (1U << 20) -/* Note that the RESERVED bits include bit 21, which is PSTATE_SS in - * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use - * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, - * where it is live state but not accessible to the AArch32 code. - */ -#define CPSR_RESERVED (0x7U << 21) #define CPSR_J (1U << 24) #define CPSR_IT_0_1 (3U << 25) #define CPSR_Q (1U << 27) |