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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-08-31 09:45:14 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-08-31 09:45:14 +0100 |
| commit | 851ec6eba56d0153574c042bff05a3d0f235a00e (patch) | |
| tree | 8f28ffb5276c55c6214fdd300a8df395dfa2f1dd /target/arm/cpu.h | |
| parent | ae4acc696f34bf0cb8865521c16ff378b19915b3 (diff) | |
| download | focaccia-qemu-851ec6eba56d0153574c042bff05a3d0f235a00e.tar.gz focaccia-qemu-851ec6eba56d0153574c042bff05a3d0f235a00e.zip | |
target/arm: Allow cpu to configure GM blocksize
Previously we hard-coded the blocksize with GMID_EL1_BS. But the value we choose for -cpu max does not match the value that cortex-a710 uses. Mirror the way we handle dcz_blocksize. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230811214031.171020-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a1e604366b..278cc135c2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1075,6 +1075,8 @@ struct ArchCPU { /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ uint8_t dcz_blocksize; + /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ + uint8_t gm_blocksize; uint64_t rvbar_prop; /* Property/input signals. */ |