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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-07-14 14:23:01 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-07-18 13:20:13 +0100 |
| commit | 988cc1909f2895cb751fc9cc83ba51938be02183 (patch) | |
| tree | 72731a3f0eaba947d83ff7af6c1e57cec45cd7de /target/arm/cpu.h | |
| parent | afbb181c2deb4584666be17adfbc49532fc90ace (diff) | |
| download | focaccia-qemu-988cc1909f2895cb751fc9cc83ba51938be02183.tar.gz focaccia-qemu-988cc1909f2895cb751fc9cc83ba51938be02183.zip | |
target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_t
Change the representation of the VSTCR_EL2 and VTCR_EL2 registers in the CPU state struct from struct TCR to uint64_t. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220714132303.1287193-6-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6afcc882f2..b14c7c3eec 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -340,8 +340,8 @@ typedef struct CPUArchState { uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ /* MMU translation table base control. */ TCR tcr_el[4]; - TCR vtcr_el2; /* Virtualization Translation Control. */ - TCR vstcr_el2; /* Secure Virtualization Translation Control. */ + uint64_t vtcr_el2; /* Virtualization Translation Control. */ + uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ uint32_t c2_data; /* MPU data cacheable bits. */ uint32_t c2_insn; /* MPU instruction cacheable bits. */ union { /* MMU domain access control register |