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authorRichard Henderson <richard.henderson@linaro.org>2022-06-20 10:51:52 -0700
committerPeter Maydell <peter.maydell@linaro.org>2022-06-27 11:18:17 +0100
commita3637e8882f9dbb00036ff77a88b841bd2580900 (patch)
treeed5b8dda8291d86f3df4abbe721731945344ab72 /target/arm/cpu.h
parentd5b1223ac1ddf8f706f5e6feaaa526df8287f8b1 (diff)
downloadfocaccia-qemu-a3637e8882f9dbb00036ff77a88b841bd2580900.tar.gz
focaccia-qemu-a3637e8882f9dbb00036ff77a88b841bd2580900.zip
target/arm: Add PSTATE.{SM,ZA} to TB flags
These are required to determine if various insns
are allowed to issue.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
-rw-r--r--target/arm/cpu.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index dec52c6c3b..05d369e690 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3160,6 +3160,8 @@ FIELD(TBFLAG_A64, TCMA, 16, 2)
 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)
+FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)
+FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
 
 /*
  * Helpers for using the above.