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authorAlex Bennée <alex.bennee@linaro.org>2017-02-23 18:29:27 +0000
committerAlex Bennée <alex.bennee@linaro.org>2017-02-24 10:32:46 +0000
commitca759f9e387db87e1719911f019bc60c74be9ed8 (patch)
tree5d328bd7b1c22749e282991182ddd1644e291fab /target/arm/cpu.h
parent4881658a4bf6dc5335e5033d0916b2e86687463d (diff)
downloadfocaccia-qemu-ca759f9e387db87e1719911f019bc60c74be9ed8.tar.gz
focaccia-qemu-ca759f9e387db87e1719911f019bc60c74be9ed8.zip
tcg: enable MTTCG by default for ARM on x86 hosts
This enables the multi-threaded system emulation by default for ARMv7
and ARMv8 guests using the x86_64 TCG backend. This is because on the
guest side:

  - The ARM translate.c/translate-64.c have been converted to
    - use MTTCG safe atomic primitives
    - emit the appropriate barrier ops
  - The ARM machine has been updated to
    - hold the BQL when modifying shared cross-vCPU state
    - defer powerctl changes to async safe work

All the host backends support the barrier and atomic primitives but
need to provide same-or-better support for normal load/store
operations.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Pranith Kumar <bobby.prani@gmail.com>
Reviewed-by: Pranith Kumar <bobby.prani@gmail.com>
Diffstat (limited to 'target/arm/cpu.h')
-rw-r--r--target/arm/cpu.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index e285ba3b4b..38a8e00908 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -30,6 +30,9 @@
 #  define TARGET_LONG_BITS 32
 #endif
 
+/* ARM processors have a weak memory model */
+#define TCG_GUEST_DEFAULT_MO      (0)
+
 #define CPUArchState struct CPUARMState
 
 #include "qemu-common.h"