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authorPeter Maydell <peter.maydell@linaro.org>2021-08-16 19:03:04 +0100
committerPeter Maydell <peter.maydell@linaro.org>2021-08-26 17:02:01 +0100
commitcc7613bfaa1f653a6eb6ff50ac45d5c5fd717052 (patch)
tree542ec7f1f8e56ec4555ecd4c8fa3c4a173b6632e /target/arm/cpu.h
parent665cddbe15fdc5f5c66caac62472bd5af1e23e10 (diff)
downloadfocaccia-qemu-cc7613bfaa1f653a6eb6ff50ac45d5c5fd717052.tar.gz
focaccia-qemu-cc7613bfaa1f653a6eb6ff50ac45d5c5fd717052.zip
target/arm: Implement HSTR.TTEE
In v7, the HSTR register has a TTEE bit which allows EL0/EL1 accesses
to the Thumb2EE TEECR and TEEHBR registers to be trapped to the
hypervisor. Implement these traps.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210816180305.20137-2-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
-rw-r--r--target/arm/cpu.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 1060825c74..0cd3206041 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1541,6 +1541,8 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 #define SCR_ENSCXT            (1U << 25)
 #define SCR_ATA               (1U << 26)
 
+#define HSTR_TTEE (1 << 16)
+
 /* Return the current FPSCR value.  */
 uint32_t vfp_get_fpscr(CPUARMState *env);
 void vfp_set_fpscr(CPUARMState *env, uint32_t val);