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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-06-08 19:38:54 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-06-08 19:38:54 +0100 |
| commit | f45ce4c35f5e0873bbbc3119eff8539610233b7e (patch) | |
| tree | 28e00c540fdb80e6ea4bafe0619ee783a4a28315 /target/arm/cpu.h | |
| parent | 5e79887ba67e22bfd890b72f94c482176a200fbc (diff) | |
| download | focaccia-qemu-f45ce4c35f5e0873bbbc3119eff8539610233b7e.tar.gz focaccia-qemu-f45ce4c35f5e0873bbbc3119eff8539610233b7e.zip | |
target/arm: Rename TBFLAG_A64 ZCR_LEN to VL
With SME, the vector length does not only come from ZCR_ELx. Comment that this is either NVL or SVL, like the pseudocode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0ee1705a4f..e791ffdd6b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3241,7 +3241,8 @@ FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ */ FIELD(TBFLAG_A64, TBII, 0, 2) FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) -FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) +/* The current vector length, either NVL or SVL. */ +FIELD(TBFLAG_A64, VL, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ |