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authorRichard Henderson <richard.henderson@linaro.org>2020-07-20 10:25:36 +0100
committerPeter Maydell <peter.maydell@linaro.org>2020-07-20 11:35:15 +0100
commit6f4e1405b91da0d0a1084ae3aff2bd308432778f (patch)
tree8a719b20945a96a970dea2a10aa4915edb6f3ba7 /target/arm/cpu64.c
parent873ec69aeb12e24eec7fb317fd0cd8494e8489dd (diff)
downloadfocaccia-qemu-6f4e1405b91da0d0a1084ae3aff2bd308432778f.tar.gz
focaccia-qemu-6f4e1405b91da0d0a1084ae3aff2bd308432778f.zip
hw/arm/virt: Enable MTE via a machine property
Control this cpu feature via a machine property, much as we do
with secure=on, since both require specialized support in the
machine setup to be functional.

Default MTE to off, since this feature implies extra overhead.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200713213341.590275-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu64.c')
-rw-r--r--target/arm/cpu64.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 15494002d2..dd696183df 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -646,8 +646,9 @@ static void aarch64_max_initfn(Object *obj)
         t = cpu->isar.id_aa64pfr1;
         t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
         /*
-         * Begin with full support for MTE; will be downgraded to MTE=1
-         * during realize if the board provides no tag memory.
+         * Begin with full support for MTE. This will be downgraded to MTE=0
+         * during realize if the board provides no tag memory, much like
+         * we do for EL2 with the virtualization=on property.
          */
         t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);
         cpu->isar.id_aa64pfr1 = t;