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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-06-20 10:51:56 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-06-27 11:18:17 +0100 |
| commit | 7f9e25a6e43356d4a0fb2cc201c1a45c5be5bb6c (patch) | |
| tree | ce63c2296f231e37184fdbf01b3cb9a410ee5b01 /target/arm/cpu64.c | |
| parent | 531cc510370eb7f672eaca416b0a3927806b3983 (diff) | |
| download | focaccia-qemu-7f9e25a6e43356d4a0fb2cc201c1a45c5be5bb6c.tar.gz focaccia-qemu-7f9e25a6e43356d4a0fb2cc201c1a45c5be5bb6c.zip | |
target/arm: Create ARMVQMap
Pull the three sve_vq_* values into a structure. This will be reused for SME. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu64.c')
| -rw-r--r-- | target/arm/cpu64.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a46e40f4f2..cadc401c7e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -355,8 +355,8 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * any of the above. Finally, if SVE is not disabled, then at least one * vector length must be enabled. */ - uint32_t vq_map = cpu->sve_vq_map; - uint32_t vq_init = cpu->sve_vq_init; + uint32_t vq_map = cpu->sve_vq.map; + uint32_t vq_init = cpu->sve_vq.init; uint32_t vq_supported; uint32_t vq_mask = 0; uint32_t tmp, vq, max_vq = 0; @@ -369,14 +369,14 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) */ if (kvm_enabled()) { if (kvm_arm_sve_supported()) { - cpu->sve_vq_supported = kvm_arm_sve_get_vls(CPU(cpu)); - vq_supported = cpu->sve_vq_supported; + cpu->sve_vq.supported = kvm_arm_sve_get_vls(CPU(cpu)); + vq_supported = cpu->sve_vq.supported; } else { assert(!cpu_isar_feature(aa64_sve, cpu)); vq_supported = 0; } } else { - vq_supported = cpu->sve_vq_supported; + vq_supported = cpu->sve_vq.supported; } /* @@ -534,7 +534,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) /* From now on sve_max_vq is the actual maximum supported length. */ cpu->sve_max_vq = max_vq; - cpu->sve_vq_map = vq_map; + cpu->sve_vq.map = vq_map; } static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, @@ -595,7 +595,7 @@ static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name, if (!cpu_isar_feature(aa64_sve, cpu)) { value = false; } else { - value = extract32(cpu->sve_vq_map, vq - 1, 1); + value = extract32(cpu->sve_vq.map, vq - 1, 1); } visit_type_bool(v, name, &value, errp); } @@ -611,8 +611,8 @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, return; } - cpu->sve_vq_map = deposit32(cpu->sve_vq_map, vq - 1, 1, value); - cpu->sve_vq_init |= 1 << (vq - 1); + cpu->sve_vq.map = deposit32(cpu->sve_vq.map, vq - 1, 1, value); + cpu->sve_vq.init |= 1 << (vq - 1); } static bool cpu_arm_get_sve(Object *obj, Error **errp) @@ -974,7 +974,7 @@ static void aarch64_max_initfn(Object *obj) cpu->dcz_blocksize = 7; /* 512 bytes */ #endif - cpu->sve_vq_supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); + cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); aarch64_add_pauth_properties(obj); aarch64_add_sve_properties(obj); @@ -1023,7 +1023,7 @@ static void aarch64_a64fx_initfn(Object *obj) /* The A64FX supports only 128, 256 and 512 bit vector lengths */ aarch64_add_sve_properties(obj); - cpu->sve_vq_supported = (1 << 0) /* 128bit */ + cpu->sve_vq.supported = (1 << 0) /* 128bit */ | (1 << 1) /* 256bit */ | (1 << 3); /* 512bit */ |