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| author | Peter Collingbourne <pcc@google.com> | 2021-06-16 12:56:14 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-24 14:58:48 +0100 |
| commit | 86f0d4c7290eb2b21ec3eb44956ec245441275db (patch) | |
| tree | 7e9e77a5ac5bb39227615ab6a9f814d0c0e91563 /target/arm/cpu64.c | |
| parent | 4f57ef959cf83cc780658c7e97ba5f737aa666f2 (diff) | |
| download | focaccia-qemu-86f0d4c7290eb2b21ec3eb44956ec245441275db.tar.gz focaccia-qemu-86f0d4c7290eb2b21ec3eb44956ec245441275db.zip | |
target/arm: Implement MTE3
MTE3 introduces an asymmetric tag checking mode, in which loads are checked synchronously and stores are checked asynchronously. Add support for it. Signed-off-by: Peter Collingbourne <pcc@google.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210616195614.11785-1-pcc@google.com [PMM: Add line to emulation.rst] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu64.c')
| -rw-r--r-- | target/arm/cpu64.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1c23187d1a..c7a1626bec 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -683,7 +683,7 @@ static void aarch64_max_initfn(Object *obj) * during realize if the board provides no tag memory, much like * we do for EL2 with the virtualization=on property. */ - t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); cpu->isar.id_aa64pfr1 = t; t = cpu->isar.id_aa64mmfr0; |