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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-10-21 17:01:31 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-10-27 10:27:23 +0100 |
| commit | e4c93e44ab103f6c67abd85d620343f61aafa004 (patch) | |
| tree | 29ff31acaafd54705245a67e216b2e0cca8fc3e3 /target/arm/cpu64.c | |
| parent | 344744e148e6e865f5a57e745b02a87e5ea534ad (diff) | |
| download | focaccia-qemu-e4c93e44ab103f6c67abd85d620343f61aafa004.tar.gz focaccia-qemu-e4c93e44ab103f6c67abd85d620343f61aafa004.zip | |
target/arm: Implement FEAT_E0PD
FEAT_E0PD adds new bits E0PD0 and E0PD1 to TCR_EL1, which allow the
OS to forbid EL0 access to half of the address space. Since this is
an EL0-specific variation on the existing TCR_ELx.{EPD0,EPD1}, we can
implement it entirely in aa64_va_parameters().
This requires moving the existing regime_is_user() to internals.h
so that the code in helper.c can get at it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221021160131.3531787-1-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu64.c')
| -rw-r--r-- | target/arm/cpu64.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 85e0d1daf1..da95eabab5 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1185,6 +1185,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ + t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ cpu->isar.id_aa64mmfr2 = t; t = cpu->isar.id_aa64zfr0; |