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authorPeter Maydell <peter.maydell@linaro.org>2020-09-01 16:51:37 +0100
committerPeter Maydell <peter.maydell@linaro.org>2020-09-01 16:51:37 +0100
commit8d90bfc5c31ad60f6049dd39be636b06bc00b652 (patch)
tree5af66a13ed5b0057351741ae6c548458b8728e08 /target/arm/helper-a64.c
parent071a6dba7d4db57e28f659b30829b1c22b945f4e (diff)
parent3f462bf0f6ea6382dd1502d4eb1fcd33c8e774f5 (diff)
downloadfocaccia-qemu-8d90bfc5c31ad60f6049dd39be636b06bc00b652.tar.gz
focaccia-qemu-8d90bfc5c31ad60f6049dd39be636b06bc00b652.zip
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200901' into staging
target-arm queue:
 * Implement fp16 support for AArch32 VFP and Neon
 * hw/arm/sbsa-ref: add "reg" property to DT cpu nodes
 * hw/arm/sbsa-ref : Add embedded controller in secure memory

# gpg: Signature made Tue 01 Sep 2020 16:17:23 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200901: (47 commits)
  hw/arm/sbsa-ref : Add embedded controller in secure memory
  hw/misc/sbsa_ec : Add an embedded controller for sbsa-ref
  hw/arm/sbsa-ref: add "reg" property to DT cpu nodes
  target/arm: Enable FP16 in '-cpu max'
  target/arm: Implement fp16 for Neon VMUL, VMLA, VMLS
  target/arm/vec_helper: Add gvec fp indexed multiply-and-add operations
  target/arm/vec_helper: Handle oprsz less than 16 bytes in indexed operations
  target/arm: Implement fp16 for Neon VRINTX
  target/arm: Implement fp16 for Neon VRINT-with-specified-rounding-mode
  target/arm: Implement fp16 for Neon VCVT with rounding modes
  target/arm: Implement fp16 for Neon VCVT fixed-point
  target/arm: Convert Neon VCVT fixed-point to gvec
  target/arm: Implement fp16 for Neon float-integer VCVT
  target/arm: Implement fp16 for Neon pairwise fp ops
  target/arm: Implement fp16 for Neon VRSQRTS
  target/arm: Implement fp16 for Neon VRECPS
  target/arm: Implement fp16 for Neon fp compare-vs-0
  target/arm: Implement fp16 for Neon VFMA, VMFS
  target/arm: Implement fp16 for Neon VMLA, VMLS operations
  target/arm: Implement fp16 for Neon VMAXNM, VMINNM
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper-a64.c')
-rw-r--r--target/arm/helper-a64.c11
1 files changed, 0 insertions, 11 deletions
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 8682630ff6..030821489b 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -234,17 +234,6 @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
  * versions, these do a fully fused multiply-add or
  * multiply-add-and-halve.
  */
-#define float16_two make_float16(0x4000)
-#define float16_three make_float16(0x4200)
-#define float16_one_point_five make_float16(0x3e00)
-
-#define float32_two make_float32(0x40000000)
-#define float32_three make_float32(0x40400000)
-#define float32_one_point_five make_float32(0x3fc00000)
-
-#define float64_two make_float64(0x4000000000000000ULL)
-#define float64_three make_float64(0x4008000000000000ULL)
-#define float64_one_point_five make_float64(0x3FF8000000000000ULL)
 
 uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
 {