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| author | Jerome Forissier <jerome.forissier@linaro.org> | 2022-10-04 09:23:54 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-10-10 14:52:23 +0100 |
| commit | 06f2adccfa26be55237ac966c376a42c52efb299 (patch) | |
| tree | c4bc2f969cdd3058c5b6fae0d4b1296f182ea7e7 /target/arm/helper.c | |
| parent | bbde13cd14ad4eec18529ce0bf5876058464e124 (diff) | |
| download | focaccia-qemu-06f2adccfa26be55237ac966c376a42c52efb299.tar.gz focaccia-qemu-06f2adccfa26be55237ac966c376a42c52efb299.zip | |
target/arm: allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented
Updates write_scr() to allow setting SCR_EL3.EnTP2 when FEAT_SME is
implemented. SCR_EL3 being a 64-bit register, valid_mask is changed
to uint64_t and the SCR_* constants in target/arm/cpu.h are extended
to 64-bit so that masking and bitwise not (~) behave as expected.
This enables booting Linux with Trusted Firmware-A at EL3 with
"-M virt,secure=on -cpu max".
Cc: qemu-stable@nongnu.org
Fixes: 78cb9776662a ("target/arm: Enable SME for -cpu max")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221004072354.27037-1-jerome.forissier@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index db3b1ea72d..c08a7b35a0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1752,7 +1752,7 @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Begin with base v8.0 state. */ - uint32_t valid_mask = 0x3fff; + uint64_t valid_mask = 0x3fff; ARMCPU *cpu = env_archcpu(env); /* @@ -1789,6 +1789,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_doublefault, cpu)) { valid_mask |= SCR_EASE | SCR_NMEA; } + if (cpu_isar_feature(aa64_sme, cpu)) { + valid_mask |= SCR_ENTP2; + } } else { valid_mask &= ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { |