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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-09-16 07:22:13 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-09-25 15:42:34 +0100 |
| commit | 166e7990566bcfe49e2a68443ea314a1ef7066a9 (patch) | |
| tree | e31f214bcd4a2765c05efb8ebc43087db201f138 /target/arm/helper.c | |
| parent | 5470f91ad19d051202d4d6931185f6a56b627c81 (diff) | |
| download | focaccia-qemu-166e7990566bcfe49e2a68443ea314a1ef7066a9.tar.gz focaccia-qemu-166e7990566bcfe49e2a68443ea314a1ef7066a9.zip | |
target/arm: Drop define_one_arm_cp_reg_with_opaque
The last use of this interface was removed in 603bc048a27f
("hw/arm: Remove pxa2xx_pic"). As the comment in gicv3
stated, keeping pointer references to cpregs has SMP issues,
so avoid future temptation by removing the interface.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 29 |
1 files changed, 11 insertions, 18 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 7b23e7e588..b76a0edb0f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7355,12 +7355,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) } /* - * Private utility function for define_one_arm_cp_reg_with_opaque(): + * Private utility function for define_one_arm_cp_reg(): * add a single reginfo struct to the hash table. */ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, - void *opaque, CPState state, - CPSecureState secstate, + CPState state, CPSecureState secstate, int crm, int opc1, int opc2, const char *name) { @@ -7448,9 +7447,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, r2->opc2 = opc2; r2->state = state; r2->secure = secstate; - if (opaque) { - r2->opaque = opaque; - } if (make_const) { /* This should not have been a very special register to begin. */ @@ -7555,8 +7551,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, } -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *r, void *opaque) +void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) { /* * Define implementations of coprocessor registers. @@ -7715,7 +7710,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, if (nxs_ri.fgt) { nxs_ri.fgt |= R_FGT_NXS_MASK; } - add_cpreg_to_hashtable(cpu, &nxs_ri, opaque, state, + add_cpreg_to_hashtable(cpu, &nxs_ri, state, ARM_CP_SECSTATE_NS, crm, opc1, opc2, name); } @@ -7729,17 +7724,17 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, switch (r->secure) { case ARM_CP_SECSTATE_S: case ARM_CP_SECSTATE_NS: - add_cpreg_to_hashtable(cpu, r, opaque, state, + add_cpreg_to_hashtable(cpu, r, state, r->secure, crm, opc1, opc2, r->name); break; case ARM_CP_SECSTATE_BOTH: name = g_strdup_printf("%s_S", r->name); - add_cpreg_to_hashtable(cpu, r, opaque, state, + add_cpreg_to_hashtable(cpu, r, state, ARM_CP_SECSTATE_S, crm, opc1, opc2, name); g_free(name); - add_cpreg_to_hashtable(cpu, r, opaque, state, + add_cpreg_to_hashtable(cpu, r, state, ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->name); break; @@ -7751,7 +7746,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, * AArch64 registers get mapped to non-secure instance * of AArch32 */ - add_cpreg_to_hashtable(cpu, r, opaque, state, + add_cpreg_to_hashtable(cpu, r, state, ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->name); } @@ -7762,12 +7757,10 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, } /* Define a whole list of registers */ -void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs, - void *opaque, size_t len) +void define_arm_cp_regs_len(ARMCPU *cpu, const ARMCPRegInfo *regs, size_t len) { - size_t i; - for (i = 0; i < len; ++i) { - define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque); + for (size_t i = 0; i < len; ++i) { + define_one_arm_cp_reg(cpu, regs + i); } } |