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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-05-24 18:02:27 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-05-25 16:01:43 +0100 |
| commit | 2dc10fa2f900fbb6fa5573c6c9411145b3a166f9 (patch) | |
| tree | 9bce3095adb3aab5fff0798a8beeb55664f96abd /target/arm/helper.c | |
| parent | 2fed21d25b3a95628698825d682d7386c5a08ae2 (diff) | |
| download | focaccia-qemu-2dc10fa2f900fbb6fa5573c6c9411145b3a166f9.tar.gz focaccia-qemu-2dc10fa2f900fbb6fa5573c6c9411145b3a166f9.zip | |
target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2
Will be used for SVE2 isa subset enablement. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 59e9847133..a66c1f0b9e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7879,8 +7879,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - /* At present, only SVEver == 0 is defined anyway. */ - .resetvalue = 0 }, + .resetvalue = cpu->isar.id_aa64zfr0 }, { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST, |