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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-06-20 10:52:03 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-06-27 11:18:17 +0100 |
| commit | 5d7953adcfb30196ba684d3af69271528630367f (patch) | |
| tree | aaca7c487f23e2990a7ef3441769ad7da25a170f /target/arm/helper.c | |
| parent | 6ca54aa9a882ece5a6bcf5879f25bdcd7a95331f (diff) | |
| download | focaccia-qemu-5d7953adcfb30196ba684d3af69271528630367f.tar.gz focaccia-qemu-5d7953adcfb30196ba684d3af69271528630367f.zip | |
target/arm: Add SVL to TB flags
We need SVL separate from VL for RDSVL et al, as well as ZA storage loads and stores, which do not require PSTATE.SM. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 2e4e739969..d2886a123a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11352,7 +11352,13 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); } if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { - DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el)); + int sme_el = sme_exception_el(env, el); + + DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el); + if (sme_el == 0) { + /* Similarly, do not compute SVL if SME is disabled. */ + DP_TBFLAG_A64(flags, SVL, sve_vqm1_for_el_sm(env, el, true)); + } if (FIELD_EX64(env->svcr, SVCR, SM)) { DP_TBFLAG_A64(flags, PSTATE_SM, 1); } |