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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-08-31 09:45:15 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-08-31 09:45:15 +0100 |
| commit | 6d482423fcecb34056013268fa552b1ce2efcfeb (patch) | |
| tree | 5044ae30a81fd7360597b3dc768326bd68c1421d /target/arm/helper.c | |
| parent | d8100822d6988cf7837aa780eaa24de6752b1c59 (diff) | |
| download | focaccia-qemu-6d482423fcecb34056013268fa552b1ce2efcfeb.tar.gz focaccia-qemu-6d482423fcecb34056013268fa552b1ce2efcfeb.zip | |
target/arm: Apply access checks to neoverse-n1 special registers
Access to many of the special registers is enabled or disabled by ACTLR_EL[23], which we implement as constant 0, which means that all writes outside EL3 should trap. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230811214031.171020-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 4dfc51de35..e3f5a7d2bd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -319,8 +319,8 @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, } /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ -static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) +CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) { if (arm_current_el(env) == 1) { uint64_t trap = isread ? HCR_TRVM : HCR_TVM; |